For a high speed serial digital communication system that transports a series of data symbols over time, one significant distortion source is inter-symbol interference (ISI) due to the non-ideal transfer function of the channel between the transmitter and receiver. ISI is a form of symbol interference from adjacent symbols which degrades the bit error rate (BER) performance of the system. One common mitigation technique against ISI is the employment of an equalizer in an active stage of the receiver. Input signals received at input/output (I/O) pads of a chip are passed through a front end of the receiver in the chip, which typically includes AC-coupling networks to remove the common mode (CM) level in the input signals before further processing the signals using an equalizer in the active stage of the receiver. In the active stage of the receiver, the equalizer can compensate for the non-ideal transfer function of the channel in order to mitigate ISI. Different types of equalizers may be used. One particular form of equalizer is known as a decision feedback equalizer (DFE), where a plurality of weighted delay line outputs are combined to provide an improved receiver response. The weights are determined by bit decisions at the receiver output which are feedback to the receiver input.
If the channel loss is limited, 1-tap DFEs (i.e., a DFE using a single offset injection element) may be employed to negate the effects of the first post cursor. One common way for adding the tap-1 coefficient to the data signals is by injection using a summing stage. A typical summing stage includes active transistor stages, such as resistive or capacitively loaded summers, dual-port samplers, etc. FIGS. 1A and 1B show a conventional resistively loaded summing stage in a DFE and a conventional capacitively loaded summing stage in another DFE, respectively.
Referring to FIG. 1A, the DFE 100 includes an input stage 110 having a pair of transistors to receive a differential signal pair (IN and IN_bar) at the gates of the transistors. The drains of the transistors are connected to a pair of resistors 120. The drains of the transistors are further connected to one or more summing stages 130 (only one summing stage is shown in FIG. 1A to avoid obscuring the illustration). Each summing stage 130 receives a tap (H1 and H1_bar), also referred to as an offset injection element. Each summing stage 130 actively injects an offset from the tap into the input signal pair to generate a pair of output signals at the drains of the transistors. However, such scheme results in an output settling time that correlates to a product of the resistance of the resistor 120 and the capacitance of the wire in the circuitry (i.e., RC time constant). Another drawback of the DFE 100 is high power consumption due to the large bias currents for the input stage 110 and the summing stages 130.
FIG. 1B shows another conventional DFE 150, which replaces the resistors 120 with a pair of resettable capacitors 160, implemented with a pair of p-type Metal Oxide Semiconductor (pMOS) transistors. By replacing the resistors 120 with the capacitors 160, the RC settling time of the outputs can be eliminated. However, the drawback of high power consumption due to the large bias currents for the input stage 110 and the summing stages 130 remains.
Furthermore, the above schemes can suffer linearity or compression issues when injecting large magnitudes of offset. Thus, there is a need in the art for improved 1-tap DFEs that are more power efficient and provides better linearity even when injecting large magnitude of offsets.